[컴퓨터구조] #18. Virtual Memory(2)

 

Lec 18. Virtual Memory_2 (Large and Fast: Exploiting Memory Hierarchy)

 

- Translation Lookaside Buffer (TLB)
  : page table이 main memory 안에 저장되어있기 때문에,
    memory access 할 때마다 적어도 두 번 메모리 접근 해야함.
   (page table 접근하여 VA->PA 할 때, 명령어나 데이터 가져올 때)

   => page table entry를 갖고있는 cache인 TLB를 사용.
        (VA->PA를 위해 메인메모리까지 가지 않아도 됨)

 

 

- TLB Structure
Let’s assume that, Virtual address is 32-bit wide, Physical address is 30-bit wide.
Just like caches, the TLB can be organized as direct mapped, set associative, or fully associative

ex1) Direct-mapped TLB with 8 entries (4KB pages)

ex2) 4-way set associative with 128 entries

 

 

- TLB Terminology

  • TLB hit
    : An accessed page by CPU is present in TLB

  • TLB miss 
    : An accessed page by CPU is not present in TLB

     1) Merely TLB miss
        : If the page is already loaded into main memory,
         then the TLB miss can be handled (in hardware or software) by loading the translation information
         from the page table(main memory) into the TLB. 시간 적게 걸림

      2) Page fault
         : If the page is not in main memory(swap에 있음), it’s called page fault.
          The requested page is transferred from hard-disk to main memory via DMA(Direct Memory Access)
          시간 엄청 오래 걸림(흔하지는 않음)

 

- TLB Structure

  즉, page가 evict될때의 dirty bit 관리 필요 (hard-disk update 위해)
  -> TLB에서 관리함

 

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- TLB and Page Table

 

- TLB and Cache Interaction

VA -> PA -> Cache -> Data